july 1998 fds892 8a dual n & p-channel enhancement mode field effect transistor general description features absolute maximum ratings t a = 25c unless otherwise noted symbol parameter n-channel p-channel units v dss drain-source voltage 3 0 -20 v v gss gate-source voltage 8 -8 v i d drain current - continuous (note 1a) 5.5 -4 a - pulsed 20 -20 p d power dissipation for dual operation 2 w power dissipation for single operation (note 1a) 1.6 (note 1b) 1 (note 1c) 0.9 t j ,t stg operating and storage temperature range -55 to 150 c thermal characteristics r q ja thermal resistance, junction-to-ambient (note 1a) 78 c/w r q jc thermal resistance, junction-to-case (note 1) 40 c/w fds892 8a rev. b soic-16 sot-23 supersot t m -8 so-8 sot-223 supersot t m -6 these dual n- and p -channel enhancement mode power field effect transistors are produced using fairchild 's proprietary, high cell density, dmos technology. this very high density process is especially tailored to minimize on-state resistance and provide superior switching performance. these devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed. n-channel 5.5 a,3 0 v, r ds(on ) =0.030 w @ v gs =4.5 v r ds(on ) =0.038 w @ v gs =2.5 v. p-channel - 4 a, -20 v, r ds(on ) = 0.055 w @ v gs =-4.5 v r ds(on ) =0.072 w @ v gs =-2.5 v . high density cell design for extremely low r ds(on) . high power and current handling capability in a widely used surface mount package. dual (n & p-channel) mosfet in surface mount package. s1 d1 s2 g1 so-8 d2 d2 d1 g2 fds 8928a pin 1 3 5 7 8 2 1 4 1 6 ? 1998 fairchild semiconductor corporation
electrical characteristics (t a = 25c unless otherwise noted) symbol parameter conditions type min typ max units off characteristics bv dss drain-source breakdown voltage v gs = 0 v, i d = 250 a n-ch 30 v v gs = 0 v, i d = -250 a p-ch -20 v d bv dss / d t j breakdown voltage temp. coefficient i d = 250 a , referenced to 25 o c n-ch 32 mv/ o c i d = -250 a , referenced to 25 o c p-ch -23 i dss zero gate voltage drain current v ds = 24 v, v gs = 0 v n-ch 1 a v ds = -16 v, v gs = 0 v p-ch -1 a i gssf gate - body leakage, forward v gs = 8 v, v ds = 0 v all 100 na i gssr gate - body leakage, reverse v gs = -8 v, v ds = 0 v all -100 na on characteristics (note 2 ) v gs (th) gate threshold voltage v ds = v gs , i d = 250 a n-ch 0.4 0.67 1 v v ds = v gs , i d = -250 a p-ch -0.4 -0.6 -1 v d v gs(th) / d t j gate threshold voltage temp. coefficient i d = 250 a , referenced to 25 o c n-ch -3 mv/ o c i d = -250 a , referenced to 25 o c p-ch 4 r ds(on) static drain-source on-resistance v gs = 4.5 v, i d = 5.5 a n-ch 0.025 0.03 w v gs = 2 .5 v, i d = 4.5 a 0.031 0.038 v gs = -4.5 v, i d = -4 a p -ch 0.043 0.055 v gs = -2 .5 v, i d = -3.4 a 0.059 0.072 i d (on) on-state drain current v gs = 4.5 v, v ds = 5 v n-ch 20 a v gs = -4.5 v, v ds = -5 v p-ch -20 g fs forward transconductance v ds = 5 v, i d = 5.5 a n-ch 20 s v ds = -5 v, i d = -4 a p-ch 13 s dynamic characteristics c iss input capacitance v ds = 10 v, v gs = 0 v, f = 1.0 mhz n-ch 900 pf p-ch 1130 c oss input capacitance n-ch 410 pf v ds = -10 v, v gs = 0 v, f = 1.0 mhz p-ch 480 c rss reverse transfer capacitance n-ch 110 pf p-ch 120 fds892 8a rev. b
electrical characteristics (continued ) switching ch aracteristics (note 2) symbol parameter conditions type min typ max units t d(on ) turn - on delay time v ds = 6 v, i d = 1 a n-ch 6 12 ns v gs = 4.5 v , r gen = 6 w p-ch 8 16 t r turn - on rise time n-ch 19 31 ns p-ch 23 37 t d(off) turn - off delay time v ds = -10 v, i d = -1 a n-ch 42 67 ns v gs = -4.5 v , r gen = 6 w p-ch 260 360 t f turn - off fall time n-ch 13 24 ns p-ch 90 125 q g total gate charge v ds = 10 v, i d = 5.5 a, n-ch 19.8 28 nc v gs = 4.5 v p-ch 20 28 q gs gate-source charge n-ch 2 nc v ds = -5 v, i d = -4 a, p-ch 2.8 q gd gate-drain charge v gs = -5 v n-ch 6.3 nc p-ch 3.2 drain-source diode characteristics and maximum ratings i s maximum continuous drain-source diode forward current n-ch 1.3 a p-ch -1.3 a v sd drain-source diode forward voltage v gs = 0 v, i s = 1.3 a (note 2) n-ch 0.68 1.2 v v gs = 0 v, i s = -1.3 a (note 2) p-ch -0.7 -1.2 v notes: 1 . r q ja is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. r q jc is guaranteed by design while r q ca is determined by the user's board design. scale 1 : 1 on letter size paper 2. pulse test: pulse width < 300 s, duty cycle < 2.0%. . fds892 8a rev. b c. 13 5 o c/w on a 0.003 in 2 pad of 2oz copper. b . 12 5 o c/w on a 0.02 in 2 pad of 2oz copper. a . 78 o c/w on a 0.5 in 2 pad of 2oz copper.
fds892 8a rev. b typical electrical characteristics: n-channel figure 1. on-region characteristics . figure 2. on-resistance variation with drain current and gate voltage . figure 5 . transfer characteristics. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 1.8 t , junction temperature (c) drain-source on-resistance j v = 4.5 v gs i = 5.5 a d r , normalized ds(on) 1 2 3 4 5 0 0.025 0.05 0.075 0.1 v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) 25c i = 3a d t = 125c a 0 0.5 1 1.5 2 2.5 3 0 4 8 12 16 20 v , gate to source voltage (v) i , drain current (a) gs 25c 125c v =5v ds d t = -55c a 0 0.2 0.4 0.6 0.8 1 1.2 0.0001 0.001 0.01 0.1 1 20 v , body diode forward voltage (v) i , reverse drain current (a) t = 125c a 25c -55c v = 0v gs sd s figure 6 . body diode forward voltage varia tion with source current and temperature. 0 6 12 18 24 30 0.8 1.2 1.6 2 i , drain current (a) drain-source on-resistance v = 2.0v gs d r , normalized ds(on) 2.5 v 4.5v 3.0v 3.5 v figure 3 . on-resistance variation with temperature . figure 4 . on-resistance variation with gate-t o -source voltage. 0 1 2 3 4 5 0 6 12 18 24 30 v , drain-source voltage (v) i , drain-source current (a) ds d 2.5v 1.5v 3.0v 2.0v v = 4.5v gs
fds892 8a rev. b typical electrical characteristics: n-channel (continued) figure 10 . single pulse maximum power dissipation. figure 8. capacitance characteristics . figure 7 . gate charge characteristics. figure 9. maximum safe operating area. 0 5 10 15 20 25 0 1 2 3 4 5 q , gate charge (nc) v , gate-source voltage (v) g gs i = 5.5a d 10v 15v v = 5v ds 0.1 0.2 0.5 1 2 5 10 20 30 50 0.01 0.03 0.1 0.3 1 3 10 50 v , drai n-source voltage (v) i , drain current (a) ds d rds(on) limit v = 4.5v single pulse r =135 c/w t = 25c gs a q ja dc 1s 10ms 100ms 10s 1ms 100us 0.1 0.4 1 2 5 10 30 30 80 200 500 1000 3000 v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0v gs c oss c rss 0.01 0.1 0.5 10 50 100 300 0 5 10 15 20 25 30 single pulse time (sec) power (w) single pulse r =135 c/w t = 25c q ja a
fds892 8a rev. b typical electrical characteristics: p-channel figure 11. on-region characteristics . figure 12. on-resistance variation with drain current and gate voltage . figure 13. on-resistance variation with temperature . figure 15 . transfer characteristics. figure 14 . on-resistance variation with gate-t o -source voltage. -50 -25 0 25 50 75 100 125 150 0.6 0.8 1 1.2 1.4 1.6 t , junction temperature (c) drain-source on-resistance j r , normalized ds(on) v = -4.5v gs i = -4.0a d 0 1 2 3 4 5 0 6 12 18 24 30 - v , drain-source voltage (v) -i , drain-source current (a) ds d - 2.5v -3.5v -3.0v -2.0v v = -4.5v gs -1.5v 0 6 12 18 24 30 0.8 1.2 1.6 2 -i , drain current (a) drain-source on-resistance v = - 2.0v gs d r , normalized ds(on) -3.0 v -4.5v -3.5v -2.5 v 0 1 2 3 4 5 0 0.05 0.1 0.15 0.2 -v , gate to source voltage (v) gs r , on-resistance (ohm) ds(on) 25c i = -2a d t = 125c a 0.4 0.8 1.2 1.6 2 0 2 4 6 8 10 -v , gate to source voltage (v) - i , drain current (a) v = -5v ds gs d 125c 25c t = -55c j 0 0.2 0.4 0.6 0.8 1 1.2 0.001 0.01 0.1 1 3 10 -v , body diode forward voltage (v) - i , reverse drain current (a) 25c -55c v = 0v gs sd s t =125c j figure 16 . body diode forward voltage varia tion with source current and temperature.
fds892 8a rev. b typical electrical characteristics: p-channel (continued) figure 2 0 . single pulse maximum power dissipation. figure 18 . capacitance characteristics . figure 17 . gate charge characteristics. figure 19. maximum safe operating area. 0 4 8 12 16 20 0 1 2 3 4 5 q , gate charge (nc) -v , gate-source voltage (v) g gs v = -5v ds -10v -15v i =-4.0a d 0.1 0.2 0.5 1 2 5 10 20 30 50 0.01 0.03 0.1 0.3 1 5 10 20 50 - v , drain-source voltage (v) - i , drain current (a) rds(on) limit d dc ds 1s 100ms 10ms 1ms 10s a v = -4.5v single pulse r = 135c/w t = 25c q ja gs a 100us 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000 2000 3000 -v , drain to source voltage (v) capacitance (pf) ds c iss f = 1 mhz v = 0 v gs c oss c rss 0.01 0.1 0.5 10 50 100 300 0 5 10 15 20 25 30 single pulse time (sec) power (w) single pulse r =135 c/w t = 25c q ja a
fds892 8a rev. b 0.0001 0.001 0.01 0.1 1 10 100 300 0.001 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 t , time (sec) transient thermal resistance r(t), normalized effective 1 single pulse d = 0.5 0.1 0.05 0.02 0.01 0.2 duty cycle, d = t /t 1 2 t - t = p * r (t) q ja a j p(pk) t 1 t 2 r (t) = r(t) * r r = 135 c/w q ja q ja q ja figure 2 1 . transient thermal response curve . thermal characterization performed using the conditions described in note 1 . transient thermal response will change depending on the circuit board design. typical thermal characteristics: n & p-channel (continued)
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